The present invention relates to digital-to-analog converters (“DACs”), and more particularly to the operation of DACs in a master-slave configuration where the master DAC is a high-precision, static DAC driving many dynamically-operated slave DACs. This master-slave configuration preserves silicon area in high-density applications.
DACs are used in applications where an analog value (e.g. current or voltage) needs to be set by means of a digital code at the input of the DAC. The analog value may be used to determine an operation point of an analog circuit. The requirements for DACs are dependent on their application and may encompass features such as high speed, high accuracy and resolution, low power or small area.
A typical current-mode DAC (“IDAC”) 100 is shown in FIG. 1. It consists of M identical static IDAC cells 101 that share a common memory block 102. A single IDAC consists of N binary weighted transistors 103 that are controlled by a code stored in the memory block 102. The binary weighted currents sum at the common output node and the resulting output current I0 has a resolution of 2−N. The gates of the turned on transistors 103 are connected to vref in order to keep them in a saturation region so that each transistor 103 can act as current source. The IDAC 100 shown in FIG. 1 is one example of many possible IDAC topologies. To assure linear operation across the entire current range, it might be necessary to replace the binary weights by thermometer-coded weights or a mixture of thermometer-coded most significant bits (MSBs) and binary coded least significant bits (LSBs).
From a surface area point of view, the typical IDAC 100 has at least two drawbacks that limit the integration density. First, each of the M identical static IDAC cells 101 needs N digital control lines. The total number of M×N control lines occupies a significant amount of wiring resources. Second, the area of a single M identical static IDAC cell 101 doubles with every additional bit of resolution. Since the area penalty scales with the factor M. Despite their robust and straight-forward design, M identical static IDAC cells 101 are not well suited for a high integration density.